The present invention relates to semiconductor memory devices and, more particularly, to nonvolatile memory devices, computing system incorporating such devices and method of operation of such devices.
An increasing number of electronic apparatuses employ nonvolatile memory devices. For example, nonvolatile memory devices are widely used as storage components in digital cameras, mobile phones, camcorders, flash memory cards, and solid state drives (SSD).
Nonvolatile memories include flash memories. Generally, flash memory devices have nonvolatile characteristics and are capable of electrically programming and erasing data. With recent demands for large capacity and high access speed in applications as large-capacity storage units or code memories, flash memories have become of great interest.
Flash memory devices can be usually classified into NAND and NOR types. A typical NAND flash memory device includes a memory cell array formed of floating-gate transistors. The memory cell array includes pluralities of memory blocks. Each memory block includes strings (hereinafter referred to as ‘NAND string’) of floating-gate transistors. Each string includes a string selection transistor, a ground selection transistor, and a plurality of memory cells connected between the string and ground selection transistors. Typically, a plurality of word lines is arranged to intersect the strings. Each word line is coupled to control gates of floating-gate cell transistors of the strings it crosses.
A cell array of a typical NOR flash memory device has a structure where a plurality of memory cells is coupled to a bit line. Comparatively, NOR flash memory devices may operate faster than NAND flash memory devices in programming and reading modes. Therefore, the NOR flash memory devices are widely employed in applications requiring high-speed operations. However, NOR flash memory devices commonly provide lower integration density than NAND flash memory devices. To overcome storage capacity limits, multi-level cells (hereinafter referred to as ‘MLC’) have been adopted for such storage elements. An MLC is able to store multi-bit data, which may overcome physical limits of integration density.
FIG. 1 is a graphic diagram showing threshold voltage distributions of multi-level cells storing 2 bits (MSB and LSB) and data values corresponding thereto. Referring to FIG. 1, the data values of the MLCs ‘11’, ‘01’, ‘10’, and ‘00’ correspond to respective threshold voltages in order. A programming operation begins from ‘11,’ corresponding to an erased state.
The memory cell is programmed to have one of the four states ‘11’, ‘01’, ‘10’, and ‘00’ in correspondence with threshold voltage distribution. First will be described a procedure for programming the least significant bit (LSB). Based on the LSB, the threshold voltage of a memory cell is maintained in the erased state or changed to a level corresponding to the state ‘10’. For instance, a threshold voltage of the memory cell is maintained in the erased state if the LSB data is ‘1’, or is raised to a threshold value corresponding to the state ‘10’ if the LSB data is ‘0’.
The most significant bit (MSB) is programmed next. A memory cell in the state ‘10’ is programmed to have the state ‘00’ or the state ‘10’ based on the MSB. In particular, the memory cell in the state ‘10’ is programmed to have the state ‘00’ if the MSB data is ‘0’ or programmed to have the state ‘10’ if the MSB data is ‘1’. A memory cell in the state ‘11’ is maintained therein or programmed to have the state ‘01’ based on the MSB. In particular, the memory cell in the state ‘11’ is programmed to have the state ‘01’ if the MSB data is ‘0’ or is maintained in the state ‘11’ if the MSB data is ‘1’. In this manner, multi-bit data may be programmed into a unit memory cell. In sum, the LSB is first programmed, followed by programming of the MSB.
However, as semiconductor memory devices are gradually advanced in integration density, interference between memory cells are becoming an issue. Such interference can cause threshold voltages of memory cells that have been programmed to be changed by application of a program voltage to other memory cells adjacent thereto. Such a change in threshold voltage can result in a corresponding change in data. Such a variation of threshold voltage may be especially troublesome in an MLC because intervals between threshold voltage ranges corresponding to different data values in MLCs typically are narrower in comparison to such intervals in single-level cells (SLCs). For that reason, it is desirable to reduce variation of threshold voltage arising from such interference.